The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices.
In a semiconductor fabrication process, it may be desirable to form recesses in the semiconductor substrate. However, traditional isotropic/v-shaped recesses in the substrate are generally not applied to 32 angstrom devices and below and generally do lead to poor device performance such as, poor junction leakage performance, and severe Si pull back after an SiGe epitaxy growth. In addition, a lightly doped drain (LDD) at a surface of the substrate under the gate has a high cutout. Thus, it is desirable to have a bottle-neck shaped recess in a semiconductor device to improve upon the disadvantages discussed above.